While the explosion of generative AI created a parallel boom in semiconductor needs, it also massively strained the existing supply chain and changed the way engineers and executives approached their businesses. At the same time, the demise of Moore’s law is putting a squeeze on the performance potential of processors.

To explore how the future of semiconductor fabrication will affect the technology we use every day, WIRED’s Greg Williams, deputy global editorial director, sat down with physicist Christian Leirer, SCHOTT’s head of Semicon Glass Solutions, and Colin Schmucker, SCHOTT Semicon Glass Solutions business development manager. Six industry insiders joined them for an invite-only executive roundtable held at WIRED’s inaugural The Big Interview conference.

Riding the AI Wave

Guests represented a diverse array of experiences from across the semiconductor ecosystem, which spanned from engineering to business development and capital investment. The hour-long conversation primarily focused on how chip manufacturers and their clients are responding to the increased demand for AI chips—and how that demand is putting pressure on the manufacturers and their engineers to eke out greater levels of performance from the existing labyrinth of chip standards.

Because the surge in AI-enabled electronics is pushing the limits of the current manufacturing capabilities, Williams kicked off the conversation by asking Leirer and Schmucker of SCHOTT for their perspectives on the role that advanced materials take in meeting these challenges. “We’re at the end of Moore’s law, and with that coming to an end, we need to find new ways to boost semiconductor performance,” Leirer said. Moore’s law is the observation from Gordon Moore’s 1965 paper that postulates that circuit density doubles every two years. But technology is such that we’re approaching a point where, because of the size of an atom, semiconductors are as small as they can get in their current form.

That’s putting more emphasis on not only how chips are fabricated (the frontend), but the backend packaging—how chips are combined to function. So while chip manufacturers are limited in how much smaller transistors can be shrunk, performance bumps are achieved through packaging and combining various functions and specifications. “It's an interesting time,” said Schmucker. “We're obviously a glass company, so we're approaching this from a very specific material mindset, but in terms of spend and advising our clients, the focus is really on backend packaging.”

Other experts in the room tackled the question from a different perspective, with the group noting that much of the meta discussion around processors has been on the final product: cutting-edge frontier AI models. However, out in the marketplace, attendees are seeing increasing demand for “n-1” technologies (products that are just below the top of the line) that are less resource intensive to build and deploy than some of the “flashier” marquee products, like the GPUs used in training AI models. After all, when the initial exuberance of new technology fades, organizations that have boards with a fiduciary responsibility to shareholders will be interested in how these products have been implemented and their relative return on investment.

The discussion highlighted that in the interim, one of the best use cases has been implementing AI in data centers, but in that case, there is the question of energy management. Optimizing for better heat management and energy efficiency goes all the way down to the processors, and when you’re trying to fit an exponential amount of processing power into a vanishingly small amount of square millimeters, it causes other issues related to memory access, power, and more. Once again, the business opportunity comes back to packaging those semiconductors.

It’s a Question of Packaging

When asked how we can improve chip performance and energy use as semiconductors continue to shrink, “packaging” was the common throughline. There is a drive for new standards and a hope that engineers design to client demand, as the current landscape of competing standards has been a point of tension. As always, the equation comes down to cost—there are less gains to be made in silicon chips, but developing new materials is costly and marginal gains are hard to justify in the short term (like most enterprise expenditures). “Silicon will reach the end of its runway eventually,” Schmucker said. “Do we continue to do modest acceleration on silicon, or do we explore other materials?”

This is why the move to glass as a material for semiconductor packaging could benefit the industry. "The inherent material properties and design freedom offered by glass make it an ideal material to address advanced packaging needs," Leirer said. The unique properties of glass provide versatile solutions for semiconductor manufacturing and components, from packaging, carrier wafers, and substrates. It can support handling the increasing data processing needs in AI applications, and the next-generation substrate technology can bring a leap forward in chip performance, achieving up to 40 percent more speed, and significantly reducing energy consumption.

Looking to the Future

In the early days of Silicon Valley, hardware companies were common, but in a business ecosystem where investors are accustomed to the relatively low capital cost of software development, hardware development and materials science is a tall order. If the largest S-curve of growth in the hardware world was going from the computer to the smartphones form factor, the latest leap has been Chip on Wafer on Substrate with silicon interposer platforms. But a combination of leading-edge materials, such as a move to glass substrates, in combination with open models and AI development will continue to surprise experts as development is accelerated—and it was clear that the assembled experts were excited to see (and build) the next generation of processors.